This invention relates generally to nanodevice assemblies, and more particularly to apparatus having a plurality of nanodevices arranged with nanoscale spacing.
The fabrication of device assemblies such as integrated circuits is continually evolving with a view to reducing dimensions and improving performance. Modern computer chips are typically fabricated using semiconductor “nanodevices”, i.e. devices which have at least one dimension on the nanoscale (from a fraction of a nanometer up to hundreds of nanometers).
Nanodevices in integrated circuits generally warm up during operation. Since such devices typically have strongly temperature-dependent behavior, this can be detrimental to performance. Memory cells provide a particular example of such nanodevices. A typical memory chip comprises one or more integrated arrays of memory cells arranged in rows and columns. It is important to ensure that heat generated by individual cells cannot disturb the state of neighboring cells and so cause data errors on readback. This “thermal disturb” issue is particularly problematical where active heating of cells is fundamental to cell operation. In phase-change memory (PCM) for example, a cell can be set to different resistive states, representing different stored information, by heating a volume of chalcogenide material in the cell to different temperatures. The chalcogenide can be set to one or more wholly or partially crystalline states by heating to appropriate temperatures. The chalcogenide can then be reset to an amorphous state by heating to a higher temperature, causing melting of the chalcogenide. For this RESET operation, the active cell volume needs to be heated above a melting temperature of typically about 900 K. The temperature of neighboring cells must, however, remain below the chalcogenide crystallization temperature, typically about 450 K, to avoid thermal disturb. With increasingly higher storage densities, the distance between memory cells will decrease below 20 nm. Tailoring the steep temperature gradients between cells poses one of the main challenges in scaling down PCM technology.
Current measures to counter heating problems in nanodevice assemblies involve either incorporating insulating layers to protect vulnerable devices, or providing conducting channels to convey heat away via thermal conduction. In memory arrays, for instance, layers of thermally insulating material such as Si3N4 have been incorporated between memory cells, dramatically reducing thermal conduction between neighboring cells.